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Case Studies & Testimonials
Nvidia discusses their successful evaluation of a methodology for completing clock domain crossing verification by linkings CDC static sign-off and simulation. Real Intent Meridian CDC and the Meridian CDC Simportal feature were deployed.
Dream Chip discusses how they implemented a multipolicy methodology using Real Intent Ascent Lint to reduce engineering verification time.
HCLTech shares their advanced methodology for early checking of connection integrity at the RTL & netlist level for blocks and top-level designs. HCL successfully applied this methodology to verify connectivity & glitches on an active SoC design using Real Intent SafeConnect in a few days, versus several weeks work required with alternative methods.
Kinara’s shift Left DFT sign-off methodology for edge AI processor using Real Intent Meridian DFT. The case study covers Kinara’s advanced DFT sign-off methodology to ensure their AI processor has high quality DFT-ready RTL and high fault coverage, while meeting tight delivery timeframes.
STMicroelectronics presented a case study on their domain crossing policies, with a goal for full CDC/RDC coverage, no design bugs, and no waivers unless there was proper justification. They ran Real Intent Meridian RDC and a competitive tool on a dual CPU subsystem with 150,000 gates, 15 clock domains, ~25,000 CDC paths and ~450,000 RDC paths. Meridian RDC achieved a 25X reduction in noise, and a ~4X reduction in runtime and RAM usage.
This case study covers Google’s cloud-based static sign-off methodology that includes pre-submit with RTL Linting, Single-mode & Multimode clock domain crossing & Reset domain crossing.
The results he presents include improved engineering efficiency and bugs found.
Samsung, Nvidia,
Esperanto, Groq
Static Sign-Off Symposium 2023 Proceedings. Speakers from Samsung, Nvidia, Esperanto and Groq discussed their advanced static sign off methodologies.
Google
Nvidia
Samsung
Static Sign-Off Best Practices DAC Panel Proceedings. Panelists from Google, Nvidia and Samsung discussed their static sign off goals, their selected best practices and technologies used to support those goals, and their results in accelerating early functional verification & sign-off of digital designs.
Samsung discusses how they implemented their advanced dynamic clock domain crossing verification methodology for memory design using Real Intent Meridian CDC Simportal, closing the sign-off gap between CDC static sign-off and simulation.
Hailo successful static sign-off for edge AI processor using Real Intent Meridian CDC & Ascent Lint. Includes: Ascent Lint shortened their verification time an estimated five weeks by reducing simulation debug. Additionally, Hailo was able to get good quality results from Meridian CDC within the first two weeks. Also, the ease of integration of IP vendor constraints avoided noise in CDC runs.
By implementing an advanced dynamic CDC verification methodology with Meridian CDC, Samsung successfully proved that additional functional errors associated with metastability can be precisely identified with design-aware dynamic CDC models, in comparison with the more conventional data-transition based models, or simulation alone.
By implementing their advanced RDC methodology with reset grouping with Meridian RDC, Samsung was able to identify all the relevant issues and produce low-noise results for their low-power SoC design.
Samsung achieved an 86 percent reduction in violation report noise with their new RDC sign-off methodology as compared with their prior approach.
Western Digital’s enhanced constraint-driven clock domain crossing (CDC) sign-off methodology with Real Intent Meridian CDC, as presented at the 2021 Design Automation Conference, achieved a two-thirds to a three-quarters reduction in total CDC sign-off time, achieving sign-off in only two weeks, compared with a typical six to eight weeks.
Nvidia clock domain crossing CDC handshake advanced sign-off methodology minimizes the additional engineering effort required to complete full CDC sign-off, by ensuring unsafe scenarios are consistently identified within Real Intent Meridian CDC’s full violation report. This article summarizes the methodology and results shown in the DAC presentation.
Dream Chip
“For the initial SOC, we needed two weeks, and the derivative only took two days. We found and fixed two CDC issues with Meridian CDC. As for CDC results logic with DFT — there we found one issue which was a CDC error in a DFT interface bridge. In the end, we successfully completed our CDC analysis of DFT logic.” – Herbert Blesse, Dream Chip
“Ascent AutoFormal enabled a 30 percent reduction in logic simulation time. This simulation reduction was based on AutoFormal’s ability to identify the root cause error as a primary failure, with other violations detected as warnings.” – Atsunori Machida, Fujitsu Kyushu Network Technologies
SK Hynix presented a case study on SK Hynix’s advanced reset domain crossing methodology and verification at the Design Automation conference, using Real Intent Meridian RDC (reset domain crossing), showing that using proactive methodology with the right set of static RDC sign-off tools reduced SK Hynix’ RDC verification effort from 2 weeks to only 25 mins. This article summaries their findings.
“Meridian RDC‘s engine is specifically customized for RDC. This makes Meridian RDCs reports much simpler to go through. 9x fewer false violations [vs. a competitor’s RDC tool] make for a more efficient debug process for us.
“The Meridian RDC runtime was 3x to 4x faster than the [competitor’s RDC tool] runtime for the same design.”
“We set up a new hierarchical CDC flow using [Real Intent Meridian CDC]. …We have very complex clock structures and large designs. The runtime with the hierarchical flow is so good, designers can have 2-3 iterations of debug in 1 day. …Top CDC owners saved roughly 75% of effort with this new flow.” – Youngchan (YC) Lee, Samsung
“The install and bring up for Real Intent’s Ascent Lint was extremely easy. We were able to deploy it with one engineer, and it took only one to two days to get to actionable data. Ascent Lint’s performance was fast, plus its outputs were clear and obvious — the ease of interpretation of results spoke to a mature tool. We look forward to using Ascent Lint on all of our future projects.” – Ty Garibay, VP of Engineering, Mythic
“We selected Real Intent’s solution because of the clear accuracy and debug advantages over other options. We determined that the adoption of [Ascent AutoFormal] in our flow will contribute to improved quality of LSI designs for our communication systems. Being able to automatically analyze RTL early in the design cycle, without the need to write assertions or test-benches, was key to our decision. The smart reporting of Ascent AutoFormal greatly reduced the size of analysis results compared to other tools and provided equal or better accuracy of results. These advanced debugging capabilities help our designers debug in a short amount of time, and reduce design errors and turnaround time for our product development.” – Katsuhisa Ikeuchi, Network Platform Development Division, NEC
The capability of reading/using multi-mode SDC (design constraints) of STA for running CDC in multi-mode elevates Meridian CDC to a sign-off tool. …One common report for multi-mode CDC would prevent the duplication of common errors (CDC violations) across multiple modes, hence this saves the user’s time to debug the common CDC violations in each mode.” – User review
“We selected Real Intent’s Meridian CDC solution because of its distinct accuracy, capacity and reporting advantages over our previous methodology. Finding asynchronous crossing errors and having the excellent accuracy of the analysis reports were key to our decision. Meridian was able to detect actual design failures and yet did not report false failures. Its efficiency in reporting the exact re-convergence points in our designs, and the formal analysis of possible pulse-width errors also proved the accuracy of the tool.” – Kenji Aoshima, General Manager Information Systems Products Business Unit, Hitachi Metals
“What we use Ascent Lint for is to identify where the designer’s intent deviates from his/her code. It can look at a particular structure and say: I see what you’re doing, but this is what’s actually going to happen… It might be something as subtle as a width mismatch, such as trying to assign a 64-bit quantity only 62 bits, and then discovering that two bits are missing. Or inferred latches.” – User review
“Meridian RDC‘s speed was good. Our IP Block was a complex DSP engine — and took only 19 minutes to run. …The feedback from the tool was pretty straight forward, and it was relatively low noise vs. our other tool. The tool identified ~ 3000 paths in the design that had safe crossings due to proper clock gating. 1000 metastable crossing cases with issues due to deprecated partial async domain handling in RTL. 700 were due to a soft reset feature being added to the IP which needed to be flushed out.” – User review
“NVIDIA has been a customer of Real Intent since 2000. We are extremely happy with the products, they are a regular part of our flows, and the quality of technical support is excellent. Real Intent is a reliable business partner for us because of their friendly business practice and dedication to make their customers successful.” – Dan Smith, Director of Hardware Engineering, NVIDIA
Western Digital developed an enhanced clock & reset verification methodology to make the Meridian CDC static sign-off tool aware of Western Digital’s clock and reset architectures. The results were: 1) They exponentially reduced their CDC sign-off noise and debug effort, and 2) They caught corner-case reset synchronization issues because only real violations were flagged with the enhanced methodology.
“We are using Meridian CDC for a specific reason. …We want to verify larger designs above the block level. The interfaces are more interesting (vulnerable to CDC problems) between blocks, and verifying larger pieces of the chip at once means fewer setups that we need to create. In this larger scope of verification, we also want to use more complex sign-off constraints (from STA), and more complex clocking structures in the design. Basically, we want to model and constrain the design for CDC in a way close to the way we sign it off.” – User review
“Real Intent Meridian CDC checks RTL design for clock domain crossing issues. I found from direct experience with the tool that: 1) Meridian’s analysis is fast, running at ~4,500 gates/second; Meridian CDC automatically identifies clocks in the design which makes environment setup effortless; Meridian’s report had less noise than the Spyglass – there were fewer unnecessary structures in the Meridian report file than the equivalent Spyglass CDC report; and Real Intent Meridian CDC gives us good visibility — we can drill down in the Meridian debug database for detailed analysis at the path-level.” – User review
“Ascent AutoFormal helped find a few corner case bugs that we missed in simulation… We used to spend considerable amount of time trying to figure out how to create the right stimulus so that all lines of code was be executed. Sometimes … we’re spending lot of time and simulation cycles trying to figure out how to create the “right” stimulus to execute a block of code that cannot be reached due to a RTL bug. AutoFormal helped us find these blocks of dead code without any testbench. Using the built-in automatic assertions in AutoFormal, we were able to fix bugs at the early stage of our design phase to get 100% code coverage.” – User review
“Real Intent is low noise, it only sends out errors and warnings that are real. Lint tools in general throw out a lot of garbage, and it’s hard to sort through. Also, Ascent Lint doesn’t have duplicates, which helps a lot. Some of the other tools give the same error – with different names — double, triple, quadruple, and even 20 times.” – User review
“…Ascent Lint is very easy to run inside the Cadence Incisive environment. Within minutes of the tool getting installed we were able to run it on our IP with practically no time spent on setting up the tool. We like the incremental report generation because it identifies any additional issues when we create newer version of RTL. We also liked the lint rules in Ascent Lint that checks the use of the Synopsys full-case parallel case pragmas.” – User review