In the News

Jun 21, 2024

DeepChip: Top 3 “Must See Tools for Design Automation Conference 2024

Jun 11, 2024

EDA Cafe: Shifting left HDL validation; security sign-off & more

Jun 6, 2024

Tech Design Forums: Real Intent tool looks at paths to hardware vulnerability

May 10, 2024

EENews: lowRISC to use Real Intent tools for OpenTitan Project

May 10, 2024

Hardware Bee: lowRISC Partners with Real Intent for OpenTitan Project

May 10, 2024

Electronic Specifier: lowRISC deploys static sign-off tools for OpenTitan project

May 9, 2024

Bit Perfect: Real Intent Tools Enhance Design Sign-Off Process for Open-Source Project

Feb 2, 2024

SemiEngineering: EDA Back On Investors’ Radar

Jan 25, 2024

DeepChip: Prakash on DFT static signoff tool — plus 25 years of Real Intent

Dec 21, 2023

SemiEngineering: 2023 — A Good Year For Semiconductors

Nov 27, 2023

Semi: Growing Into a Management Role: Perspectives From Real Intent CEO Prakash Narain

Jan 23, 2023

EDACafe: Industry Predictions for 2023

Jan 12, 2023

SemiEngineering: Design And Verification Methodologies Breaking Down

Dec 29, 2022

EEJournal: Introducing SafeConnect Connectivity and Glitch Sign-Off from Real Intent

Dec 5, 2022

Semi: Chip Design & Verification’s Shift Left to Reduce Costs & Cycle Time

Nov 15, 2022

Tech Design Forum: [SafeConnect] looks for connectivity & glitches

Oct 27, 2022

Raising IP Integration Up A Level

Jun 17, 2022

Semiconductor Engineering: Week in Review [Meridian CDC & Ascent Lint]

Jun 10, 2022

Semiconductor Engineering: Week in Review [Meridian RDC]

May 12, 2022

Tech Design Forum: Extended coverage for sign-off analysis [Meridian DFT]

Dec 23, 2021

SemiEngineering Week in Review — Real Intent Joined the DARPA Toolbox Initiative

Sep 15, 2021

ESDA/Semi:  CEO Perspective — Shift Left is Driving Expanding Role of Functional Static Sign-Off

Jun 24, 2021

SemiEngineering:  CEO Outlook — More Data, More Integration, Same Deadlines

May 21, 2021

DeepChip: Users Rank Real Intent #3 in “Best of 2020” Report for: RDC, CDC, Multimode CDC, & RTL Lint

Apr 20, 2021

BTV: Reset Domain Crossing Sign-Off — 4 Fundamentals to Eliminate RDC Bug Escapes

Apr 7, 2021

Panel: Prakash on True Multimode Sign-Off vs Single Mode

Mar 26, 2021

User Evaluation Criteria & Results for Meridian RDC

Oct 16, 2020

DeepChip:  Prakash on functional static sign-off to grow 2X in 5 years to $300M

Jul 27, 2020

Challenges For A Post-Moore’s Law World

Jul 13, 2020

SemiEngineering: Maximizing Value Post-Moore’s Law

Jul 5, 2020

SemiEngineering: Chip Reliability Vs. Cost

Jun 25, 2020

EEJournal:  TNG of DFT  (“The Next Generation” of DFT)

Jun 25, 2020

SemiEngineering:  2020 CEO Outlook

Jun 20, 2020

BTV: RTL Linting Tool Reviews

Jun 12, 2020

SemiEngineering: Week in Review: Real Intent debuted Verix DFT

Jun 9, 2020

Tech Design Forum: Real Intent tries to shift left on DFT

Jun 9, 2020

EENews: Multimode DFT static sign-off tool delivers root cause analysis

Feb 20, 2020

DeepChip: Users Rank Real Intent #3 in “Best of 2019” Report for: CDC, RDC, RTL Lint & Formal Lint

Dec 19, 2019

SemiEngineering: Crossed Wires On Domains

Oct 28, 2019

SemiEngineering: Rapid Evolution For Verification Plans

Oct 7, 2019

BestTech Views:  Static Sign-Off: 6 Fundamentals to Maximize Verification Efficiency during Design

Sep 26, 2019

SemiEngineering:  Solving The Memory Bottleneck

Jul 21, 2019

SemIsrael Interview with the CEO of Real Intent

Jun 30, 2019

BestTech Views: Reset Domain Crossing Tools – Reviews

Jun 25, 2019

EENews Europe: Automated RTL verification gains 10X speed and 5X capacity increases

Jun 3, 2019

DeepChip: Real Intent “Complete CDC Sign-Off” ranks #4 on DAC 19 Must See List

Apr 18, 2019

DeepChip: User benchmark of Real Intent Meridian RDC (Reset Domain Crossing)

Jan 23, 2019

DeepChip: Users rank Real Intent #3 “Best of 2018” EDA tools

Oct 30. 2018

SemIsrael: SemIsrael Exclusive Interview with Real Intent CEO Prakash Narain

Jun 15. 2018

DeepChip: Prakash to launch gate-level CDC linter and CDC EC tools

May 24. 2018

Prakash Replies to Dan Joyce GLS with X-Pessimism Tool

Feb 21. 2018

User Survey: Real Intent Ranked #6 “Best of” for 2017

Dec 14. 2017

DAC Panel: Prakash and Anirudh discuss Real Intent vs Cadence Linting

Oct 27. 2017

DeepChip: One User’s Eval of Real Intent AutoFormal and Ascent Lint

Oct 23. 2017

DeepChip: Cliff Cummings on Real Intent

Sep 22. 2017

DeepChip: Prakash sees 3X revenue in 2017

Sep 14. 2017

EDACafe: Real Intent: Leveraging on Investments

Aug 28. 2017

EEJournal: Clocks, Xs, and Resets: Real Intent Discusses New Solutions

Jun 01. 2017

BestTech Views: Clock Domain Crossing Tools – Reviews

Apr 01. 2017

SemiWiki: Caution: Reset Domains Crossing

Feb 23. 2017

DeepChip: Prakash on DVcon 16, portable stimulus, the end of simulation

Dec 16. 2016

DeepChip: Real Intent tied for #2 overall for Best EDA of 2016

Aug 25. 2016

EDACafe: Real Intent: A sustained culture of Respect & Innovation

May 06. 2016

DeepChip: User on why he switched from Atrenta to RealIntent for lint/CDC/X

Apr 01. 2016

SiliconIndia: SiliconIndia names Real Intent in its 2016 list of 20 Most Promising Semiconductor Companies

Dec 08. 2015

EETimes: X-Pessimism: A Realistic Approach is Needed

Oct 08. 2015

DeepChip: Real Intent DAC 15 survey on CDC bugs, X propagation, constraints

Oct 22. 2015

SiliconIndia: CEO Insight: Is Silicon the New Fabric for Our Lives?

Aug 20. 2015

EETimes: The Power of Dynamic Voltage Frequency Scaling

Jul 24. 2015

EETimes: Making a Difference Still Does Make a Difference

May 16. 2015

Tech Design Forum: Technology trends demand netlist-level CDC verification

Aug 16. 2015

VerifNews: VerifNews interview with Graham Bell

Feb 25. 2015

Tech Design Forum: DO-254 without tears

Feb 25. 2015

Tech Design Forum: Real Intent updates linter for aviation, Mathworks and SystemVerilog

Jan 13. 2015

Tech Design Forum: Taking control of constraints verification

Oct 01. 2014

ChipEstimate.com: Clock-Domain Crossing Verification: Essentials To Achieve SoC Success

Oct 23. 2014

EDACafe: CTO & Visionary: A conversation with Real Intent’s Pranav Ashar

Oct 01. 2014

DeepChip: Graham Bell’s Synopsys-Verdi Interop Trip Report

Sep 30. 2014

Tech Design Forum: The evolution of lint

Jul 03. 2014

Tech Design Forum: It’s time to embrace objective-driven verification

Jun 06. 2014

Semiconductor Engineering: Experts At The Table: Where Do We Stand With CDC? Part 1

Jul 18. 2014

Semiconductor Engineering: Experts At The Table: Where Do We Stand With CDC? Part 2

Sep 29. 2014

Semiconductor Engineering: Experts At The Table: Where Do We Stand With CDC? Part 3

Apr 16. 2014

Tech Design Forum: Hierarchy provides a smarter approach to SoC CDC verification

Apr 16. 2014

Tech Design Forum: Reset optimization pays big dividends before simulation

Mar 26. 2014

Tech Design Forum: Real Intent’s Ascent XV at the ‘fuzzy’ boundary between design and verification

Feb 26. 2014

Tech Design Forum: Complexity drives smart reporting

Dec 05. 2013

Electric Engineering Journal: X-Verification Methodology for Both Designers and Verification Engineers

Nov 11. 2013

Semiconductor Engineering: Cracking The Tough Nut Using Formal Methods

Oct 24. 2013

Semiconductor Engineering: Experts At The Table: The Future Of Verification Part 1

Nov 04. 2013

Tech Design Forum: Experts At The Table: The Future Of Verification Part 2

Nov 11. 2013

Tech Design Forum: Experts At The Table: The Future Of Verification Part 3

Sep 09. 2013

EETimes: A common methodology to manage X propagation in both design and verification

Sep 13. 2013

EETimes: An Engineer’s Progress With Prakash Narain Part 1

Sep 16. 2013

EETimes: An Engineer’s Progress With Prakash Narain Part 2

Sep 19. 2013

EETimes: An Engineer’s Progress With Prakash Narain Part 3

Sep 24. 2013

EETimes: An Engineer’s Progress With Prakash Narain Part 4

Sep 05. 2013

Tech Design Forum: Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off

Jul 13. 2013

EDACafe: Prakash Narain: creating a unique workplace culture at Real Intent

Jun 09. 2013

SemiWiki.com: SoC Sign-off, Real Intent at DAC

Jun 01. 2013

DeepChip: Real Intent’s not-so-secret DVcon’13 Report

Mar 11. 2013

Tech Design Forum: Clock-domain and reset verification in the low-power design era

Aug 23. 2012

Tech Design Forum: Verification challenges require surgical precision

Apr 01. 2012

DVCon: X-Propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist

Mar 20. 2012

Tech Design Forum: Blindsided by a glitch

Feb 07. 2011

EDACafe: Real Intent – Part II

Nov 02. 2010

Chip Design: What you need to know for effective CDC Analysis?

Oct 11. 2010

EDACafe: Real Intent

May 06. 2010

Chip Design: Building Strong Foundations

Aug 08. 2009

EDA Cafe: The Role of a Chief Technology Officer

Apr 13. 2009

Chip Design: The Inevitable Change in the EDA Industry

Jun 17. 2009

EDA Confidential: Real Intent Looks to the Future

Oct 07. 2008

Chip Design: Max’s Chips and Dips: Timing Closure Verification from Real Intent

Mar 23. 2007

Chip Design: Will Timing-Exception Verification Reach Its Full Potential?

Apr 16. 2007

EETimes: Real Intent Formally verifies Clock Crossings